Technical Field
The technical field is data processing, or, more specifically, methods, apparatus, and products for aligning FIFO pointers in a data communications lane of a serial link.
Description of Related Art
In high speed serial data communications designs, data to be transmitted from a source to a target may begin provided by the source in parallel form and be transmitted to the target in serial form. In such systems the clock utilized to transmit the data in serial form is often times greater in rate than the clock which is used to provide the data in parallel form. Jitter and drift in the two separate clock signals generally causes the two clocks to operate plesio-synchronously with respect to one another, even in systems in which the clocks are based (through clock trees and the like) on the same system clock.
Some serial communications links are implemented with a number of lanes. Each such lane may include a First-in-First-Out buffer (‘FIFO’) that passes the data from the parallel side to the serial side of the transmitter. Each FIFO may include a write side and a read side. The write side of the FIFO receives data in parallel form from a source and the read side transmits the data in serial form to a target. The write side may operate on a system clock and the read side may operate on a separate clock that, like the serial clock mentioned above, is much higher in rate than the system clock. In such a system, two sets of signals utilized by each FIFO require alignment to insure that data transmitted serially is an accurate representation of the data received in parallel form. First, read and write pointers must be offset by a predetermined, or programmable amount, so the FIFO can absorb any clock phase alignment differences between the read and write clock. Second in a multiple lanes design it is important to align all the lanes to minimize the lane-to-lane skew when the data reaches the target at the other end of the serial link. In today's designs, aligning all the lanes together includes issuing a common reset to both the read and write side of the FIFO to set the correct offset for the read and write pointers. The read and write side clocks are plesio-synchronous, however. In addition, the difference in the arrival time of each lane's read clock can result in different lanes experiencing the reset in different cycles thereby causing the lanes to be skewed in an unpredictable way. If the user wishes to have the ability to have a programmable offset between the read and write pointers an additional bus would need to be synchronized into the high speed domain.